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Difference between revisions of "Template:Infobox soc"

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(Criou página com '{{Infobox | title = {{{name|<includeonly>{{PAGENAMEBASE}}</includeonly>}}} | image = {{#invoke:InfoboxImage|InfoboxImage|image={{{image|}}}|size={{{image_size|}}}|sizedefa...')
 
 
(21 intermediate revisions by the same user not shown)
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| image  = {{#invoke:InfoboxImage|InfoboxImage|image={{{image|}}}|size={{{image_size|}}}|sizedefault=frameless|alt={{{alt|}}}}}
 
| image  = {{#invoke:InfoboxImage|InfoboxImage|image={{{image|}}}|size={{{image_size|}}}|sizedefault=frameless|alt={{{alt|}}}}}
 
| caption = {{{caption|}}}
 
| caption = {{{caption|}}}
−
| header1 = {{ #if: {{{produced-end|}}}{{{produced-start|}}}{{{created|}}}{{{soldby|}}}{{{designfirm|}}}{{{manuf1|}}}{{{cpuid|}}}{{{code|}}} | General Info }}
+
| header1 = {{ #if: {{{soldby|}}}{{{designfirm|}}}{{{produced-start|}}}{{{produced-end|}}}{{{manuf1|}}}{{{cpuid|}}} | General information }}
−
| label2  = Launched
+
| label2  = Marketed by
−
| data2  = {{{produced-start|}}}{{{created|}}}<!--some pages still using created-parameter-->
+
| data2  = {{{soldby|}}}
−
| label3  = Discontinued
+
| label3  = Designed by
−
| data3  = {{{produced-end|}}}
+
| data3  = {{{designfirm|}}}
−
| label4  = Marketed by
+
| label4  = Announced
−
| data4  = {{{soldby|}}}
+
| data4  = {{{produced-start|}}}
−
| label5  = Designed by
+
| label5  = Discontinued
−
| data5  = {{{designfirm|}}}
+
| data5  = {{{produced-end|}}}
−
| label6  = Common manufacturer(s)
+
| label6  = Manufactured by
 
| data6  = {{unbulleted list
 
| data6  = {{unbulleted list
 
| {{{manuf1|}}}
 
| {{{manuf1|}}}
Line 19: Line 19:
 
| {{{manuf4|}}}
 
| {{{manuf4|}}}
 
| {{{manuf5|}}}
 
| {{{manuf5|}}}
 +
| label11 = CPUID dode
 +
| data11  = {{{cpuid|}}}
 
}}  
 
}}  
−
| label11 = [[CPUID]] code
+
| header12 = {{ #if: {{{transistors|}}}{{{transistors1|}}}{{{numcores|}}}{{{numcores1|}}}{{{gpu|}}}{{{npu|}}}{{{isp|}}}{{{dsp|}}}{{{co-processor|}}} | Specifications }}
−
| data11  = {{{cpuid|}}}
+
| label13 = Transistors
−
| label12 = Product code
+
| data13 = {{unbulleted list
−
| data12  = {{{code|}}}
 
−
| header19 = {{ #if: {{{clock|}}}{{{slowest|}}}{{{fsb|}}}{{{fsb-slowest|}}}{{{hypertransport-slowest|}}}{{{qpi-slowest|}}}{{{dmi-slowest|}}}{{{data-width|}}}{{{address-width|}}}{{{virtual-width|}}} | Performance }}
 
−
| label20 = Max. [[Central processing unit|CPU]] [[clock rate]]
 
−
| data20  = {{#if:{{{clock|}}}|{{{clock}}}<!--some pages still using this old parameter-->|{{#if:{{{slowest|}}}|{{{slowest}}}&nbsp;{{{slow-unit|GHz}}}}} {{#if:{{{fastest|}}}| to {{{fastest}}}&nbsp;{{{fast-unit|GHz}}}}}}}
 
−
| label21 = [[Front-side bus|FSB]] speeds
 
−
| data21  = {{#if:{{{fsb|}}}|{{{fsb}}}<!--some pages still using this old parameter-->|{{#if:{{{fsb-slowest|}}}|{{{fsb-slowest}}}&nbsp;{{{fsb-slow-unit|GHz}}}}} {{#if:{{{fsb-fastest|}}}| to {{{fsb-fastest}}}&nbsp;{{{fsb-fast-unit|GHz}}}}}}}
 
−
| label22 = [[HyperTransport]] speeds
 
−
| data22  = {{#if:{{{hypertransport-slowest|}}}|{{{hypertransport-slowest}}}&nbsp;{{{hypertransport-slow-unit|GT/s}}}}} {{#if:{{{hypertransport-fastest|}}}| to {{{hypertransport-fastest}}}&nbsp;{{{hypertransport-fast-unit|GT/s}}}}}
 
−
| label23 = [[Intel QuickPath Interconnect|QPI]] speeds
 
−
| data23  = {{#if:{{{qpi-slowest|}}}|{{{qpi-slowest}}}&nbsp;{{{qpi-slow-unit|GT/s}}}}} {{#if:{{{qpi-fastest|}}}| to {{{qpi-fastest}}}&nbsp;{{{qpi-fast-unit|GT/s}}}}}
 
−
| label24 = [[Direct Media Interface|DMI]] speeds
 
−
| data24  = {{#if:{{{dmi-slowest|}}}|{{{dmi-slowest}}}&nbsp;{{{dmi-slow-unit|GT/s}}}}} {{#if:{{{dmi-fastest|}}}| to {{{dmi-fastest}}}&nbsp;{{{dmi-fast-unit|GT/s}}}}}
 
−
| label25 = Data width
 
−
| data25  = {{{data-width|}}}
 
−
| label26 = Address width
 
−
| data26  = {{{address-width|}}}
 
−
| label27 = Virtual address width
 
−
| data27  = {{{virtual-width|}}}
 
−
| header29 = {{ #if: {{{l1cache|}}}{{{l2cache|}}}{{{l3cache|}}}{{{l4cache|}}}{{{llcache|}}} | Cache }}
 
−
| label30 = L1 [[CPU cache|cache]]
 
−
| data30  = {{{l1cache|}}}
 
−
| label31 = L2 cache
 
−
| data31  = {{{l2cache|}}}
 
−
| label32 = L3 cache
 
−
| data32  = {{{l3cache|}}}
 
−
| label33 = L4 cache
 
−
| data33  = {{{l4cache|}}}
 
−
| label34 = Last level cache
 
−
| data34  = {{{llcache|}}}
 
−
| header38 = {{ #if: {{{application|}}}{{{size-from|}}}{{{microarch|}}}{{{arch|}}}{{{arch1|}}}{{{instructions|}}}{{{extensions|}}}{{{extensions1|}}} | Architecture and classification }}
 
−
| label39 = Application
 
−
| data39  = {{{application|}}}
 
−
| label40 = [[Technology node|Min.&nbsp;feature&nbsp;size]]
 
−
| data40  = {{#if:{{{size-from|}}}|{{{size-from|}}} {{#if:{{{size-to|}}}| to {{{size-to}}}}}}}
 
−
| label41 = Architecture
 
−
| data41  = {{{arch1|}}}
 
−
| label42 = [[Microarchitecture]]
 
−
| data42  = {{{microarch|}}}
 
−
| label43 = [[Instruction set architecture|Instruction&nbsp;set]]
 
−
| data43  = {{{arch|}}}
 
−
| label44 = Instructions
 
−
| data44  = {{{instructions|}}}
 
−
| label45 = Extensions
 
−
| data45  = {{unbulleted list
 
−
| {{{extensions|}}}  <!-- some pages using just "extensions", some "extensions1", "extensions2", ... -->
 
−
| {{{extensions1|}}}
 
−
| {{{extensions2|}}}
 
−
| {{{extensions3|}}}
 
−
}}
 
−
| header49 = {{ #if: {{{transistors|}}}{{{transistors1|}}}{{{numcores|}}}{{{cores|}}}{{{cores1|}}}{{{gpu|}}}{{{co-processor|}}}{{{pack1|}}}{{{socket|}}}{{{sock1|}}} | Physical specifications }}
 
−
| label50 = [[Transistor count|Transistors]]
 
−
| data50 = {{unbulleted list
 
 
| {{{transistors|}}}  <!-- some pages using just "transistors", some "transistors1", "transistors2", ... -->
 
| {{{transistors|}}}  <!-- some pages using just "transistors", some "transistors1", "transistors2", ... -->
 
| {{{transistors1|}}}
 
| {{{transistors1|}}}
Line 85: Line 35:
 
| {{{transistors8|}}}
 
| {{{transistors8|}}}
 
}}
 
}}
−
| label51 = [[Multi-core (computing)|Cores]]
+
| label23 = [[ARM cores|CPU(s)]]
−
| data51 = {{unbulleted list
+
| data23 = {{unbulleted list
 
| {{{numcores|}}}
 
| {{{numcores|}}}
−
| {{{cores|}}}  <!-- some pages using just "cores", some "cores1", "cores2", ... -->
 
 
| {{{cores1|}}}
 
| {{{cores1|}}}
 
| {{{cores2|}}}
 
| {{{cores2|}}}
Line 95: Line 44:
 
| {{{cores5|}}}
 
| {{{cores5|}}}
 
}}
 
}}
−
| label53 = [[Graphics processing unit|GPU(s)]]
+
| label30 = GPU
−
| data53 = {{{gpu|}}}
+
| data30 = {{{gpu|}}}
−
| label54 = [[Co-processor]]
+
| label31 = NPU
−
| data54 = {{{co-processor|}}}
+
| data31  = {{{npu|}}}
−
| label55 = Package(s)
+
| label32 = ISP
−
| data55 = {{unbulleted list
+
| data32  = {{{isp|}}}
−
| {{{pack1|}}}
+
| label33 = DSP
−
| {{{pack2|}}}
+
| data33  = {{{dsp|}}}
−
| {{{pack3|}}}
+
| label34 = Co-processor
−
| {{{pack4|}}}
+
| data34 = {{{co-processor|}}}
−
| {{{pack5|}}}
+
| label35 = RAM
 +
| data35  = {{{ram|}}}
 +
| label36 = [[Mobile storage standards|Storage]]
 +
| data36  = {{{storage|}}}
 +
| label37 = [[Modems|Modem]]
 +
| data37 = {{unbulleted list
 +
| {{{modem1|}}}
 +
| {{{modem2|}}}
 +
| {{{modem3|}}}
 +
| {{{modem4|}}}
 +
| {{{modem5|}}}
 
}}
 
}}
−
| label56 = Socket(s)
+
| header40 = {{ #if: {{{clock|}}}{{{slowest|}}}{{{fsb|}}}{{{fsb-slowest|}}}{{{hypertransport-slowest|}}}{{{qpi-slowest|}}}{{{dmi-slowest|}}}{{{data-width|}}}{{{address-width|}}}{{{virtual-width|}}} | Performance }}
 +
| label41 = CPU maximum frequency
 +
| data41  = {{#if:{{{slowest|}}}|{{{slowest}}}&nbsp;{{{slow-unit|GHz}}}}} {{#if:{{{fastest|}}}| to {{{fastest}}}&nbsp;{{{fast-unit|GHz}}}}}
 +
| label42 = Bus speeds
 +
| data42  = {{#if:{{{fsb-slowest|}}}|{{{fsb-slowest}}}&nbsp;{{{fsb-slow-unit|GHz}}}}} {{#if:{{{fsb-fastest|}}}| to {{{fsb-fastest}}}&nbsp;{{{fsb-fast-unit|GHz}}}}}
 +
| label43 = [[HyperTransport]] speeds
 +
| data43  = {{#if:{{{hypertransport-slowest|}}}|{{{hypertransport-slowest}}}&nbsp;{{{hypertransport-slow-unit|GT/s}}}}} {{#if:{{{hypertransport-fastest|}}}| to {{{hypertransport-fastest}}}&nbsp;{{{hypertransport-fast-unit|GT/s}}}}}
 +
| label44 = [[Intel QuickPath Interconnect|QPI]] speeds
 +
| data44  = {{#if:{{{qpi-slowest|}}}|{{{qpi-slowest}}}&nbsp;{{{qpi-slow-unit|GT/s}}}}} {{#if:{{{qpi-fastest|}}}| to {{{qpi-fastest}}}&nbsp;{{{qpi-fast-unit|GT/s}}}}}
 +
| label45 = [[Direct Media Interface|DMI]] speeds
 +
| data45  = {{#if:{{{dmi-slowest|}}}|{{{dmi-slowest}}}&nbsp;{{{dmi-slow-unit|GT/s}}}}} {{#if:{{{dmi-fastest|}}}| to {{{dmi-fastest}}}&nbsp;{{{dmi-fast-unit|GT/s}}}}}
 +
| label46 = Data width
 +
| data46  = {{{data-width|}}}
 +
| label47 = Address width
 +
| data47  = {{{address-width|}}}
 +
| label48 = Virtual address width
 +
| data48  = {{{virtual-width|}}}
 +
| header49 = {{ #if: {{{application|}}}{{{size-from|}}}{{{microarch|}}}{{{arch|}}}{{{arch1|}}}{{{instructions|}}}{{{extensions|}}}{{{extensions1|}}} | Architecture and classification }}
 +
| label50 = Application
 +
| data50  = {{{application|}}}
 +
| label51 = [[Process_nodes|Process node]]
 +
| data51  = {{#if:{{{size-from|}}}|{{{size-from|}}} {{#if:{{{size-to|}}}| to {{{size-to}}}}}}}
 +
| label52 = Architecture
 +
| data52  = {{{arch1|}}}
 +
| label53 = Microarchitecture
 +
| data53  = {{{microarch|}}}
 +
| label54 = Instruction set
 +
| data54  = {{{arch|}}}
 +
| label55 = Instructions
 +
| data55  = {{{instructions|}}}
 +
| label56 = Extensions
 
| data56  = {{unbulleted list
 
| data56  = {{unbulleted list
−
| {{{socket|}}} <!-- some pages using just "socket", some "sock1", "sock2", ... -->
+
| {{{extensions|}}} <!-- some pages using just "extensions", some "extensions1", "extensions2", ... -->
−
| {{{sock1|}}}
+
| {{{extensions1|}}}
−
| {{{sock2|}}}
+
| {{{extensions2|}}}
−
| {{{sock3|}}}
+
| {{{extensions3|}}}
−
| {{{sock4|}}}
 
−
| {{{sock5|}}}
 
−
| {{{sock6|}}}
 
−
| {{{sock7|}}}
 
−
| {{{sock8|}}}
 
−
| {{{sock9|}}}
 
 
}}
 
}}
−
| header59 = {{ #if: {{{core1|}}}{{{pcode1|}}}{{{model|}}}{{{brand1|}}}{{{variant|}}} | Products, models, variants }}
+
| header60 = {{ #if: {{{l1cache|}}}{{{l2cache|}}}{{{l3cache|}}}{{{l4cache|}}}{{{llcache|}}} | Cache }}
−
| label60 = Core&nbsp;name(s)
+
| label61 = Cache L1
−
| data60 = {{unbulleted list
+
| data61 = {{{l1cache|}}}
−
| {{{core1|}}}
+
| label62 = Cache L2
−
| {{{core2|}}}
+
| data62  = {{{l2cache|}}}
−
| {{{core3|}}}
+
| label63 = Cache L3
−
| {{{core4|}}}
+
| data63  = {{{l3cache|}}}
−
| {{{core5|}}}
+
| label64 = Cache L4
−
| {{{core6|}}}
+
| data64  = {{{l4cache|}}}
−
| {{{core7|}}}
+
| label65 = Last level cache
−
| {{{core8|}}}
+
| data65  = {{{llcache|}}}
−
| {{{core9|}}}
+
| header66 = {{ #if: {{{pcode1|}}}{{{model|}}}{{{market1|}}}{{{variant|}}}{{{core1|}}}{{{pack1|}}}{{{socket|}}} | Identification }}
−
}}
+
| label67 = Product code(s)
−
| label61 = Product code name(s)
+
| data67 = {{unbulleted list
−
| data61 = {{unbulleted list
 
 
| {{{pcode1|}}}
 
| {{{pcode1|}}}
 
| {{{pcode2|}}}
 
| {{{pcode2|}}}
Line 145: Line 127:
 
| {{{pcode9|}}}
 
| {{{pcode9|}}}
 
}}
 
}}
−
| label62 = Model(s)
+
| label76 = Model(s)
−
| data62 = {{unbulleted list
+
| data76 = {{unbulleted list
 
| {{{model|}}} <!-- some pages using just "model", some "model1", "model2", ... -->
 
| {{{model|}}} <!-- some pages using just "model", some "model1", "model2", ... -->
 
| {{{model1|}}}
 
| {{{model1|}}}
Line 158: Line 140:
 
| {{{model9|}}}
 
| {{{model9|}}}
 
}}
 
}}
−
| label63 = Brand&nbsp;name(s)
+
| label86 = Marketing name(s)
−
| data63 = {{unbulleted list
+
| data86 = {{unbulleted list
−
| {{{brand1|}}}
+
| {{{market1|}}}
−
| {{{brand2|}}}
+
| {{{market2|}}}
−
| {{{brand3|}}}
+
| {{{market3|}}}
−
| {{{brand4|}}}
+
| {{{market4|}}}
−
| {{{brand5|}}}
+
| {{{market5|}}}
−
| {{{brand6|}}}
+
| {{{market6|}}}
−
| {{{brand7|}}}
+
| {{{market7|}}}
−
| {{{brand8|}}}
+
| {{{market8|}}}
−
| {{{brand9|}}}
+
| {{{market9|}}}
 +
}}
 +
| label95 = Variant(s)
 +
| data95  = {{{variant|}}}
 +
| label96 = Core name(s)
 +
| data96  = {{unbulleted list
 +
| {{{core1|}}}
 +
| {{{core2|}}}
 +
| {{{core3|}}}
 +
| {{{core4|}}}
 +
| {{{core5|}}}
 +
| {{{core6|}}}
 +
| {{{core7|}}}
 +
| {{{core8|}}}
 +
| {{{core9|}}}
 +
}}
 +
| label105 = Packaging(s)
 +
| data105  = {{unbulleted list
 +
| {{{pack1|}}}
 +
| {{{pack2|}}}
 +
| {{{pack3|}}}
 +
| {{{pack4|}}}
 +
| {{{pack5|}}}
 +
}}
 +
| label110 = Sockets(s)
 +
| data110  = {{unbulleted list
 +
| {{{socket|}}} <!-- some pages using just "socket", some "sock1", "sock2", ... -->
 +
| {{{sock1|}}}
 +
| {{{sock2|}}}
 +
| {{{sock3|}}}
 +
| {{{sock4|}}}
 +
| {{{sock5|}}}
 +
| {{{sock6|}}}
 +
| {{{sock7|}}}
 +
| {{{sock8|}}}
 +
| {{{sock9|}}}
 
}}
 
}}
−
| label69 = Variantes(s)
+
| header120 = {{ #if: {{{predecessor|}}}{{{successor|}}} | History }}
−
| data69  = {{{variant|}}}
+
| label121 = Predecessor
−
| header70 = Histórico
+
| data121 = {{{predecessor|}}}
−
| label71 = Predecessor
+
| label122 = Successor
−
| data71 = {{{predecessor|}}}
+
| data122 = {{{successor|}}}
−
| label72 = Sucessor
+
}}<noinclude>{{Infobox soc/doc}}
−
| data72 = {{{sucessor|}}}
+
</noinclude>
−
}}<noinclude></noinclude>
 

Latest revision as of 14:50, 10 November 2022

{{Infobox soc
| name           = 
| image          = 
| image_size     = 
| alt            = 
| caption        = 
<!----------------- General ----------------->
| soldby         = [[:category: BRAND processors|BRAND]]
| designfirm     = 
| produced-start = [[:category: YEAR processors|MONTH YEAR]]
| produced-end   = 
| manuf1         = [[:category: LITHOGRAPHY nm processors|TSMC/Samsung ("LITH nm")]]
| cpuid          = 
<!----------- Specifications ------------>
| transistors    =
| numcores       = 
| cores1         = x [[:category:ARM Cortex-A78 processors|ARM Cortex-A78]] @  GHz
| cores2         = x [[:category:ARM Cortex-A55 processors|ARM Cortex-A55]] @  GHz
| gpu            = 
| npu            = 
| isp            = 
| dsp            = 
| co-processor   = 
| ram            = 
| storage        = 
| modem1         = [[:category:5G processors|5G]] [[:category:4G processors|4G]] [[:category:Modemless processors|''n/a'']]
<!----------------- Performance ------------------>
| slowest        = 
| fastest        = 
| slow-unit      = 
| fast-unit      = 
| fsb-slowest    = 
| fsb-fastest    = 
| fsb-slow-unit  = 
| fsb-fast-unit  = 
| hypertransport-slowest   = 
| hypertransport-fastest   = 
| hypertransport-slow-unit = 
| hypertransport-fast-unit = 
| qpi-slowest    = 
| qpi-fastest    = 
| qpi-slow-unit  = 
| qpi-fast-unit  = 
| dmi-slowest    = 
| dmi-fastest    = 
| dmi-slow-unit  = 
| dmi-fast-unit  = 
| data-width     = 
| address-width  = 
| virtual-width  = 
<!------- Architecture -------->
| application    = [[:category:Premium mobile processors|Premium mobile]]
[[:category:Intermediate mobile processors|Intermediate mobile]]
[[:category:Basic mobile processors|Basic mobile]]
[[:category:Application processors|Application processors]]
[[:category:Server processors|Server]]
[[:category:PC & tablet processors|Personal computers]]
[[:category:TV & media player processors|TV Media player processors]]
| size-from      =  nm
| size-to        = 
| arch1          = ARM
| microarch      = 
| arch           = ARMv8.2-A (64-bit) ARMv7-A (32-bit)
| instructions   = 
| extensions     = 
<!-------------------- Cache --------------------->
| l1cache        = 
| l2cache        = 
| l3cache        = 
| l4cache        = 
| llcache        = 
<!--------- Identification ----------->
| pcode1         = <!-- pcode1..9 -->
| model1         = <!-- model1..9 -->
| market1        = <!-- market1..9 -->
| variant        = 
| core1          = <!-- core1..9 -->
| pack1          = <!-- pack1..9 -->
| sock1          = <!-- sock1..9 -->
<!------------------  History  ------------------->
| predecessor    = 
| successor      = 
}}
'''PROCESSOR NAME''' is a premium mobile processor from BRAND, announced in DATE].

== Devices ==


{{BRAND processors}}

== References ==
<small>
* [OFFICIAL SITE]
<references /></small>

[[category:YEAR processors]]
[[category:BRAND processors]]
[[category:LITHOGRAPHY nm processors]]
[[category:ARM Cortex-A78 processors]]
[[category:ARM Cortex-A55 processors]]
[[category:Custom core processors]]
[[category:5G processors]]
[[category:4G processors]]
[[category:3G processors]]
[[category:Modemless processors]]
[[category:Premium mobile processors]]
[[category:Intermediate mobile processors]]
[[category:Basic mobile processors]]
[[category:Application processors]]
[[category:Server processors]]
[[category:PC & tablet processors]]
[[category:TV & media player processors]]

Uso

{{Infobox soc
| name                      = Processor name
| image                     = An image to show in the infobox
| image_size                = Size of the image (defaults to 200px)
| alt                       = Mouse over text for the image
| caption                   = A caption for the image
<!------------- General -------------->
| soldby                    = Often, but not always, the same as the designfirm and/or manuf1
| produced-start            = When production began / Launch date
| produced-end              = When production ended / Discontinued date
| designfirm                = Often, but not always, the same as manuf1 and/or soldby
| manuf1                    = (1..5) Common manufacturers of the device
| cpuid                     = CPUID or PVR value
<!---------- Specifications ---------->
| transistors               = Number of transistors, transistor count
| numcores                  = Number of cores (2 for dual-core)
| cores1                    = Core(s) identification
| gpu                       = Integrated GPU
| npu                       = Integrated NPU
| isp                       = Integrated ISP
| dsp                       = Integrated DSP
| co-processor              = Co-processador integrado
| ram                       = RAM 
| storage                   = Compatible storage stantandards
| modem1                    = (1..5) Compatible mobile networks
<!----------- Performance ------------>
| slowest                   = Lowest maximum CPU clock
| fastest                   = Highest maximum CPU clock
| slow-unit                 = Unit for slow speed. Default: GHz
| fast-unit                 = Unit for fast speed. Default: GHz
| fsb-slowest               = Slowest FSB speed
| fsb-fastest               = Fastest FSB speed
| fsb-slow-unit             = Unit for slow speed. Default: MHz
| fsb-fast-unit             = Unit for fast speed. Default: MHz
| hypertransport-slowest    = Slowest HyperTransport speed
| hypertransport-fastest    = Fastest HyperTransport speed
| hypertransport-slow-unit  = Unit for slow speed. Default: GT/s
| hypertransport-fast-unit  = Unit for fast speed. Default: GT/s
| qpi-slowest               = Slowest QPI (QuickPath Interconnect) speed
| qpi-fastest               = Fastest QPI speed
| qpi-slow-unit             = Unit for slow speed. Default: GT/s
| qpi-fast-unit             = Unit for fast speed. Default: GT/s
| dmi-slowest               = Slowest DMI (Direct Media Interface) speed
| dmi-fastest               = Fastest DMI speed
| dmi-slow-unit             = Unit for slow speed. Default: GT/s
| dmi-fast-unit             = Unit for fast speed. Default: GT/s
| data-width                = Data bus width in bits
| address-width             = Address bus width in bits
| virtual-width             = Virtual address bus width in bits
<!------- Architecture -------------->
| application               = Main usage (Embedded, Mobile, Desktop, Server) and segment (basic, intermediate, premium)
| size-from                 = First fabrication size
| size-to                   = Second fabrication size
| arch1                     = ARM, MIPS, x86, AMD64
| microarch                 = 
| arch                      = Instruction set architecture (ISA) that the CPU implements
| instructions              = Instruction sets (or number of instructions)
| extensions                = Extensions to the instructions
<!----------- Cache ----------------->
| l1cache                   = Level 1 cache size
| l2cache                   = Level 2 cache size
| l3cache                   = Level 3 cache size
| l4cache                   = Level 4 cache size
| llcache                   = Last Level cache size
<!--------- Identification ---------->
| pcode1                    = (1..9) Product code names
| model1                    = (1..9) Model names
| market1                   = (1..9) Marketing names of the CPU
| variant                   = Variants in the same family and generation
| core1                     = (1..9) Names of the cores
| pack1                     = (1..5) Names of CPU packages
| sock1                     = (1..9) Names of the sockets that the CPU was made for
<!---------- History ---------------->
| predecessor               = What CPU came before
| successor                 = What CPU came after
}}

Examples

See also

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